49681BR

USA - Massachusetts - Boxborough

Job Description and Requirements

ASIC Physical Design, Sr Staff Engineer

Job Description:
The Digital Implementation team is seeking a highly motivated and innovative engineer who be part of the timing team working on timing flows, constraints, analysis & debug of timing issues that will enable physical design activities and will be responsible for physical design implementation of the Mixed-Signal DDR PHY IPs in various cutting edge process technologies. As an "ASIC Physical Design Engineer, II", the successful candidate will work on a variety of advanced DDR PHY developments including the latest standards in LP5x and DDR5. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers.


Responsibilities:
Tasks will include but not be limited to, scripting, debugging, testing and maintaining of timing flows and methodologies, documentation, synthesis, Place & Route, Static timing closure, constraints analysis, static and dynamic IR drop analysis, power estimation, electromigration checks and other physical verification tasks such as DRC/LVS/ERC.
The candidate will be expected to work independently to find solutions to complex design implementation issues and to analyze and suggest improvements to the design methodology and design flow.
Additional tasks will include creation of views necessary for SOC integration of the hard macros and running all required QA checks before release of these views.

Requirements
The successful candidate will have the following:

• A degree in Electrical/Electronic Engineering (or equivalent) with 3+ years of digital or physical design experience. Master's degree is preferred.
• Excellent software and scripting skills (Perl, Tcl, Python), understanding of CAD automation methods.
• Strong understanding of timing constraints and static timing analysis.
• Proven ability to handle broad responsibility for block-level digital physical design from RTL to GDSII signoff.
• Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques (ex: FinFET, 16nm, 12nm, 7nm, 5nm, 3nm).
• Experience with Synopsys tools or other equivalent tools for Synthesis, P&R, Physical verification, STA, Formal, EM/IR, DFT
• Understanding of digital logic and RTL circuit representation.
• Understanding of common design-for-test (DFT) implementation techniques.
• Understanding of signal integrity and power integrity.
• Excellent communication skills, ability to think and communicate at different levels of abstraction.

Job Category

Engineering

Country

United States

Job Subcategory

ASIC Physical Design

Hire Type

Employee

Base Salary Range

$134,000 to $202,000