Work with cross functional teams to optimize various parts of the SW stack AI Compiler, AI frameworks, device drivers, and firmware. Work on block & system level performance analysis for VLIW based AI Engine processor architecture. Bring up emerging ML models based on CNN, transformers and characterize performance. Develop and validate VLIW based processor systems on both

Execute on RTL design and coding for various sections of the processor core pipeline and related logic. Collaborate with a team of hardware and software engineers to define the high level architecture. Participate in the definition of microarchitecture of next generation high performance processor cores. Contribute to design verification, synthesis, power reduction, timin

Train and finetune LLMs/LMMs. Improve on the state of the art LLMs/LMMs.. Accelerate the training and inference speed of LLMs/LMMs. Research novel ML techniques and model architectures. Influence the direction of AMD AI platform. Publish your work at top tier venues. PREFERRED EXPERIENCE Experience in developing and debugging in Python. Experience in ML frameworks such as

Performance modeling and analysis of ML training and inference workloads across a single and multiple accelerators. In addition of exploring various tradeoff and design decision. Participate in hardware software co design for future hardware optimization on various ML workloads. Communicate and present the results of the performance analysis and modeling to stakeholders a

Working with Architects and reads documentation to understand features to be implemented and verified Block level test plan creation with the fully understanding of Design Specification UVM block level test bench creation and maintenance Block level test creation in directed and random constraints covering all features usage model and corner cases, for both function and p

Manage a team of RTL engineers Technical leadership within an RTL team, and across other core teams Identify bottlenecks and propose new features to improve Floating Point performance. Work with performance modeling team to model and study new features. Identify power and area optimizations, supporting multiple design variants Implement new features in RTL, working with p

Define product features and capabilities, close architecture, and micro architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all feat

Some of the expected responsibilities of the candidate will include System level modelling of power IPs, in time and frequency domain, using the models to predict post silicon performance against key metrics. Working with designers in silicon and package and ensure power routing is done to guarantee performance Supply noise analysis at a package and board level and workin

Maintain and drive operational and governance activities for the business group, including key forums such as Integrated Product Development reviews, Operations reviews, contract reviews, and leadership staff meetings Represent DSG and drive various corporate level operational activities for the business group, including quarterly Earnings and Guidance, Long Range Plannin

Develop/Modify tools and infrastructure used for performance analysis and studies Collaborate closely with multiple teams to deliver solutions and the technology to support them Look for the best out of the box solutions to solve problems or develop our own tools as needed PREFERRED EXPERIENCE Experience building and maintaining web applications is ideal, with a focus on

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Train and finetune LLMs, LMMs, and image/video generation models. Improve on the state of the art LLMs, LMMs, and image/video generation models. Accelerate the training and inference speed of LLMs, LMMs, and image/video generation models. Research novel ML techniques and model architectures. Influence the direction of AMD AI platform. Publish your work at top tier venues.

The candidate would be responsible for planning, designing, implementing, debugging, and optimizing compiler and SDK/Library for machine learning and 3D graphics hardware IP, as well as developing functional and stress applications. Collaborate with hardware architects and logic designers to solve functional issues, and customer support engineers to help resolve verificat

Provide successful Cache Architecture development and execution using RTL Design, Verilog HDL, and scripting. Collaborate with Cache and CPU Architects to design, document, and execute optimized high performance Cache and Routing Fabric designs. Collaborate with Physical Design to develop RTL that is optimized for physical construction and timing closure. Collaborate with

Collaborate with design, validation, and architecture teams for content coverage, test pattern development, validation, and debugging Develop test program infrastructure incorporating latest Best Known methods Solves sophisticated, novel, and non recurring problems; initiates significant changes to existing processes/ methods and leads development and implementation Ident